Silicon on insulator (SOI) ultra-thin body (UTB) devices are an attractive technology for relatively superior performance and low parasitic capacitance. UTB can also offer a multi-threshold voltage (Vt) scheme by biasing the back-plane (BP) underneath transistors. Passive device integration (e.g., resistors and capacitors) with complementary metal oxide semiconductor (CMOS) devices need integration in a bulk substrate. Therefore, both the BP and the wells need contacts landing on the bulk substrate.
Contacts for the BP and wells can have issues and challenges. For example, each contact landed on the Si bulk substrate region requires a minimum footprint of one Rx island, with a shallow or deep trench isolation structure surrounding each contact. Another challenge is that the topography for the contact landing to the bulk substrate may lead to defects and yield issues.
Additional issues in forming the contacts include after etching the SOI region to reveal a bulk substrate, there is a topology which can lead to process difficulty for downstream process steps, e.g., contact lithography/etching. One approach suggests to grow epitaxial silicon on the bulk area to the same level as the SOI, but the process complexity can lead to high cost and also epi-Si defects/bumps at the interface, causing process variability, among other issues. For example, issues concerning the formation of the BP contact structure include: (i) each back side contact landing on Si bulk region with minimum footprint of one Rx island and STI surrounding; and (ii) topography for the contact landing.